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外文翻譯---關于直接數字頻率合成器-其他專業.doc

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外文翻譯---關于直接數字頻率合成器-其他專業.doc

All About Direct Digital Synthesis What is Direct Digital Synthesis Direct digital synthesis DDS is a method of producing an analog waveformusually a sine waveby generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. Why would one use a direct digital synthesizer DDS Aren’t there other methods for easily generating frequencies The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations. Figure 1. The AD9833-a one-chip waveform generator. Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop PLL-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter DAC outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- or waveform generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy. Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator Figure 1, operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts. What are the main benefits of using a DDS DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface SPI, and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz based on a 1-GHz clock. The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program and re-program the output waveform, make DDS devices an extremely attractive solutionpreferable to less-flexible solutions comprising aggregations of discrete elements. What kind of outputs can I generate with a typical DDS device Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS. DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and sinusoidal outputs available from an AD9833. How does a DDS device create a sine wave Here’s a breakdown of the internal circuitry of a DDS device its main components are a phase accumulator, a means of phase-to-amplitude conversion often a sine look-up table, and a DAC. These blocks are represented in Figure 3. Figure 3. Components of a direct digital synthesizer. A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register tuning word. The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase angle address for the look-up table, which outputs the digital value of amplitudecorresponding to the sine of that phase angleto the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value the phase incrementwhich is determined by the binary number is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform. What do you mean by a complete DDS The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI. Let’s talk some more about the phase accumulator. How does it work Figure 4. Digital phase wheel. Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation. To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle see Figure 4. Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator provides the equally spaced angular values accompanying the vector’s linear rotation around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave. The phase accumulator is actually a modulo- M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word M. This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator n, which determines the tuning resolution of the DDS. For an n 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 reference-clock cycles increments. If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 reference-clock cycles the minimum required by Nyquist. This relationship is found in the basic tuning equation for DDS architecture where fOUT output frequency of the DDS M binary tuning word fC internal reference clock frequency system clock n length of the phase accumulator, in bits Changes to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop. As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave A phase -to - amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value 28 bits for AD9833with unneeded less-significant bits eliminated by truncationinto the sine-wave amplitude information that is presented to the 10 -bit D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5. Figure 5. Signal flow through the DDS architecture. 關于直接數字頻率合成器 什么是直接數字頻率合成器 直接數字頻率合成器(DDS)是一種通過產生一個以數字形式時變的信號,然后執行由數字至模擬轉換的方法。由于DDS設備的操作主要是數字的,它可以提供快速解決輸出頻率之間切換,優點是具有精細的頻率以及運行頻率范圍廣泛。由于設計方面和工藝技術的進步,如今DDS器件已變得非常緊湊而且功率非常小。 為什么要使用直接數字頻率合成器(DDS)難道沒有其它方法使不同頻率和配置文件能夠很容易地產生頻率 能夠準確地產生和控制波形已經成為一些行業的主要要求。無論是提供低相位噪聲的雜散性能良好的可變頻率通信,還是只需在生成的頻率上激活工業或生物醫學檢測設備的應用程序,成本低是重要的設計考慮。 設計師以相位鎖定回路(PLL)為基礎,需要非常高的頻率合成技術,以動態規劃的數字到模擬的轉換器(DAC)來產生許多可能產生的頻率,但DDS技術迅速獲得了解決頻率(或波形)產生和工業應用要求的方法,因為單芯片集成電路器件可以產生簡單的可編程的模擬輸出高分辨率和準確性的波形。 此外,在這兩個過程中不斷改進技術和設計,使成本和功耗水平前所未有的低。例如AD9833,一個基于DDS的可編程波形發生器(圖1),工作電壓5.5V與25MHz的時鐘,消耗的最大功率為30mW。 圖1 AD9833波形發生器 使用DDS有什么主要好處 對DDS的AD9833器件進行編程,如通過一個高速串行外設接口(SPI),而且只需要一個外部時鐘來生成簡單的正弦波。DDS器件現已可以產生從1到400MHz的頻率,(時鐘基于103MHz兆赫)。電源效益低,成本低,包裝單小,加上其固有的優良性能,并能夠以數字形式(和重新編程)輸出波形使DDS器件是極具吸引力的解決方案,相比不太靈活的包括分子聚合離散在內的解決方案。 一個典型的DDS的設備可以產出什么樣的輸出 DDS器件不僅限于純粹的正弦波輸出。圖2顯示了方波、三角波和正弦波輸出。 圖2 DDS輸出的矩形波-三角波-正弦波 如何使用DDS的設備創建一個正弦波 這里有一個DDS的內部電路其主要成分是相位累加器,振幅轉換(通常是正弦查找)和一個DAC。這些模塊的代表圖如圖3。 圖3 組件的直接數字合成器 DDS產生一個特定頻率的正弦波。它的頻率取決于兩個變量,參考時鐘頻率和(控制字)數字編程的頻率。 二進制數的頻率主要輸入到相位累加器。在使用正弦查找表時,用相位累加器計算一個階段(角)的地址查找表,輸出幅度的數字值對應相位角的正弦。反過來,DAC把這個數字轉換為相應值的模擬電壓或電流。要生成一個固定頻率的正弦波,恒定值(相位增量,這是由二進制數決定)被添加到時鐘周期的相位累加器。如果相位增量大,相位累加器會迅速通過正弦查找表,從而產生高頻率的正弦波。如果相位增量小,相位累加器將采取更多的步驟,因而產生較慢的波形。 完整的DDS是什么意思 D/A轉換器和一個DDS的單一芯片的整合通常被稱為一個完整的DDS的解決方案,ADI公司的普通性質DDS。讓我們說些有關累加器的知識。它是如何工作的連續時間正弦信號的角度范圍內有一個重復的階段0至2。數字的實施沒有什么不同,該計數器可以把相位累加器作為DDS的功能來執行。 圖4 數字相位輪 為了理解這一點的基本功能,將可視化的正弦波振蕩作為一個階段輪圍繞旋轉圓向量(見圖4)。每個階段輪指向對應的等效點1波周期的正弦。由于矢量旋轉的輪子,形象化的角度的正弦值產生相應的正弦波。一個車輪周圍的相速度向量,為一個常數,正弦波輸出結果為一個完整周期。相位累加器提供等距相角值隨車輪周圍的向量線性旋轉。相位累加器對應于點的波周期輸出的正弦。 相位累加器實際上是一個模- M的計數器,每次收到一個時鐘脈沖其存儲的數量遞增。遞增幅度取決于輸入字(米)。這個字形成相位步長之間的參考,它有效地設置跳過多少分左右相輪。規模越大的跳躍,相位累加器以越快的速度溢出,且其周期相當于一個正弦波。該輪在數字離散相點中,取決于分辨率的相位累加器(n),這決定了DDS的調諧。對于一個n 28位相位累加器,1 ... 0001 M值的0000會導致相位累加器溢出后228參考時鐘周期(增量)。如果M值更改為0111 ... 1111,相位累加器溢出后,將只有2參考時鐘周期(取決于奈奎斯特最低要求)。這種關系是發生在基本調整方程DDS的結構為 其中FOUT是DDS的輸出頻率 M是頻率控制字的二進制 fC是內部參考時鐘頻率(系統時鐘) n是每組長度的相位累加器位, M的值發生變化導致輸出頻率的變化。無回路的建立時間發生在一個循環鎖相內。由于輸出頻率的增加,減少樣本周期數。 由于抽樣理論決定了至少兩個周期,每樣都需要重建的輸出波形,基本的DDS輸出頻率是fC/2。 然而,對于實際應用中,輸出頻率是有限的,在一定程度改善波形質量的重建,并允許濾波輸出。當產生一個恒定的頻率,相位輸出線性增加,因此模擬波形生成本身就是一個斜坡。 試問,線性輸出波形怎樣轉化為正弦波 A相方法-振幅查找表用于轉換相位累加器的瞬時輸出值(28比特AD9833)將正弦波振幅信息,提交(10位)到D/A轉換器。DDS的結構充分利用了正弦波對稱的性質和利用的一個映射邏輯合成一個完整周期的正弦波。該相位對振幅查找表其余數據通過閱讀然后再向前,這形象地顯示在圖5。 圖5 流過DDS的信號 9

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